MIT researchers have developed a new manufacturing method that allows for the creation of more energy-efficient electronics by stacking multiple functional components on top of a single existing circuit.
In traditional circuits, the logic devices that perform calculations, such as transistors, and the memory devices that store data are built as separate components, forcing data to be passed back and forth between them, wasting energy.
This new electronics integration platform allows scientists to manufacture transistors and memory devices in one compact stack on a semiconductor chip. This reduces a lot of wasted energy and increases calculation speed.
Key to this progress are newly developed materials with unique properties and more precise manufacturing approaches that reduce the number of material defects. This allows researchers to create extremely small transistors with built-in memory that can operate faster than state-of-the-art devices while consuming less power than similar transistors.
By improving the energy efficiency of electronic devices, this new approach could help reduce rapidly increasing computational power consumption, especially in demanding applications such as generative AI, deep learning, and computer vision tasks.
“In the future, we need to minimize the amount of energy we use for AI and other data-centric computations because it’s simply not sustainable. To continue that progress, we’ll need new technologies like this integrated platform,” said Yanjie Shao, an MIT postdoc and lead author of two papers on these new transistors.
This new technology is described in two papers (one invited) presented at the IEEE International Electron Devices Meeting. Shao’s paper also includes senior author Jesús del Alamo, Donner Professor of Engineering in MIT’s Department of Electrical Engineering and Computer Science (EECS). Dimitri Antoniadis, Ray and Maria Stata Professor of Electrical Engineering and Computer Science, Massachusetts Institute of Technology; So do other researchers at MIT, the University of Waterloo, and Samsung Electronics.
turn the problem around
A standard CMOS (complementary metal oxide semiconductor) chip traditionally has a front end, where active components such as transistors and capacitors are fabricated, and a back end, which includes interconnects and other wires called metal bonds that connect the chip’s components.
However, some energy is lost as data moves between these bonds, and small shifts can degrade performance. Stacking active components reduces the distance data travels and increases the energy efficiency of the chip.
Stacking silicon transistors on top of a CMOS chip is difficult because manufacturing additional devices on the front end typically requires high temperatures that destroy the existing transistors underneath.
Researchers at MIT have developed an integrated technique that flips this problem on its head and instead stacks active components on the back end of the chip.
“If we can use this back-end platform to place additional active layers of transistors as well as interconnects, it will significantly increase the integration density of the chip and improve its energy efficiency,” Shao explains.
The researchers achieved this using a new material, amorphous indium oxide, as the active channel layer of the back-end transistor. The active channel layer is where the important functions of the transistor take place.
The unique properties of indium oxide allow extremely thin layers of this material to be “grown” on the back end of existing circuits at temperatures of only about 150 degrees Celsius without damaging the front end devices.
perfect the process
They carefully optimized the manufacturing process to minimize the number of defects in the layer of indium oxide material, which is only about 2 nanometers thick.
Some defects, known as oxygen vacancies, are necessary for the transistor to turn on, but too many defects prevent it from working properly. This optimized manufacturing process allows researchers to produce extremely small transistors that operate quickly and cleanly, eliminating much of the additional energy required to turn the transistors off and on.
Based on this approach, we also fabricated back-end transistors with integrated memory that are only about 20 nanometers in size. To do this, they added a layer of a material called ferroelectric hafnium zirconium oxide as a memory component.
These compact memory transistors demonstrated switching speeds of just 10 nanoseconds, reaching the limits of the team’s measurement equipment. This switching also requires much lower voltages than similar devices, reducing power consumption.
And because the memory transistor is so small, researchers can use it as a platform to study the fundamental physics of individual units of ferroelectric hafnium zirconium oxide.
“The deeper we understand the physics, the more we can use this material for many new applications. It uses very minimal energy and gives us a lot of flexibility in how we design devices. It could really open up a lot of new avenues for the future,” says Shao.
The researchers also worked with a team at the University of Waterloo to develop performance models for back-end transistors. This is an important step before integrating the device into larger circuits or electronic systems.
In the future, we hope to further develop these demonstrations by integrating back-end memory transistors into a single circuit. They also hope to study ways to improve transistor performance and gain greater control over the properties of the ferroelectric hafnium zirconium oxide.
“We can now build a platform of versatile electronics on the back end of a chip, enabling high energy efficiency and a wide range of functionality in very small devices. We have superior device architectures and materials, but we must continue to innovate to uncover the ultimate performance limits,” Shao said.
This research was supported in part by Semiconductor Research Corporation (SRC) and Intel. Manufacturing took place at the MIT Microsystems Technology Laboratory and the MIT.nano facility.
